Publications 
Transactions & International Journals
On how to Accelerate Iterative Stencil Loops: A Scalable Streaming-based Approach
R. CATTANEO, G. Natale, C. Sicignano, D. Sciuto, M. D. Santambrogio
Transactions on Architecture and Code Optimization (TACO)
doi > 10.1145/2842615
International Conferences
A Polyhedral Model-based Framework for Dataflow Implementation on FPGA devices of Iterative Stencil Loops
G. Natale, G. Stramondo, G. Bressana, R. Cattaneo, D. Sciuto, M. D. Santambrogio
International Conference On Computer Aided Design, 2016
Power-awareness and smart-resource management in embedded computing systems
M. D. Santambrogio, J. L. Ayala, S. Campanoni, R. CATTANEO, G. C. Durelli, M. Ferroni, A. Nacci, J. Pagan, M. Zapater M. Vallejo,
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2015
doi > 10.1109/CODESISSS.2015.7331372
Explicitly Isolating Data and Computation in High Level Synthesis: the Role of Polyhedral Framework
R. CATTANEO, G. Pallotta, D.Sciuto, M. D. Santambrogio
Accepted to appear in proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2015
doi > 10.1109/ReConFig.2015.7393304
On How to Efficiently Accelerate Brain Network Analysis on FPGA-Based Computing System
G.Gnemmi, M. Crippa, G. C. Durelli, R. CATTANEO, G. Pallotta, M. D. Santambrogio
Accepted to appear in proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2015
doi > 10.1109/ReConFig.2015.7393330
A Multiobjective Reconfiguration-Aware Scheduler for FPGA-Based Heterogeneous Architectures
E. A. Deiana, M. Rabozzi, R. CATTANEO, M. D. Santambrogio
Accepted to appear in proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2015
doi > 10.1109/ReConFig.2015.7393328
Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems
D. Pagano, M. Vuka, M. Rabozzi, R. CATTANEO, D. Sciuto, M. D. Santambrogio
Design, Automation & Test in Europe Conference & Exhibition 2015 (DATE), 2015
doi > 10.7873/DATE.2015.0806
FPGA-based design using the FASTER toolchain: the case of STM Spear development board
F. Spada, A. Scolari, G. C. Durelli, R. CATTANEO, D. N. Pnevmatikatos, G. N. Gaydadjiev, O. Pell, A. Brokalakis, W. Luk, D. Pau, D. Stroobandt, D. Sciuto, M. D. Santambrogio
International Symposium on Parallel and Distributed Processing with Applications (ISPA), 2014
doi > 10.1109/ISPA.2014.26
ThermOS: System Support for Dynamic Thermal Management of Chip Multi-Processors
F. Sironi, M. Maggio, R. CATTANEO, G. Del Nero, D. Sciuto, and M. D. Santambrogio
International Conference on Parallel Architectures and Compilation Techniques (PACT), 2013
doi > 10.1109/PACT.2013.6618802
Runtime Adaptation on Dataflow HPC Platforms
R. CATTANEO, C. Pilato, M. Mastinu, O. Kadlcek, O. Pell, and M. D. Santambrogio
NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2013
doi > 10.1109/AHS.2013.6604230
A2B: an Integrated Framework for Designing Heterogeneous and Reconfigurable Systems
C. Pilato, R. CATTANEO, G. Durelli, A. A. Nacci, M. D. Santambrogio, and D. Sciuto
NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2013
doi > 10.1109/AHS.2013.6604246
SMASH: A Heuristic Methodology for Designing Partially Reconfigurable MPSoCs
R. CATTANEO, C. Pilato, G. Durelli, M. D. Santambrogio, and D. Sciuto
IEEE International Symposium on Rapid System Prototyping (RSP), 2013 doi > 10.1109/RSP.2013.6683965
The Autonomic Operating System Project - Achievements and Future Directions
D. B. Bartolini, R. CATTANEO, G. Durelli, M. Maggio, M. D. Santambrogio, and F. Sironi
Design Automation Conference (DAC), 2013
doi > 10.1145/2463209.2488828
International Workshops
Relocation-aware Floorplanning for Partially-Reconfigurable FPGA-based Systems
M. Rabozzi, R. CATTANEO, T. Becker, W. Luk, M. D. Santambrogio
IPDPS Workshop on Reconfigurable Architectures (RAW), 2015
doi > 10.1109/IPDPSW.2015.52
K-Ways Partitioning of Polyhedral Process Networks: a Multi-Level Approach
R. CATTANEO, M. Moradmand, D. Sciuto, M. D. Santambrogio
IPDPS Workshop on Reconfigurable Architectures (RAW), 2015
doi > 10.1109/IPDPSW.2015.17
PaRA-Sched: a Reconfiguration-Aware Scheduler for Reconfigurable Architectures
R. CATTANEO, R. Bellini, G. C. Durelli, C. Pilato, and M. D. Santambrogio
IPDPS Workshop on Reconfigurable Architectures (RAW), 2014
doi > 10.1109/IPDPSW.2014.32
Adaptive Raytracing Implementation using Partial Dynamic Reconfiguration
G. C. Durelli, F. Spada, R. CATTANEO, C. Pilato, D. Pau, and M. D. Santambrogio
IPDPS Workshop on Reconfigurable Architectures (RAW), 2014
doi > 10.1109/IPDPSW.2014.31
A Framework for Effective Exploitation of Partial Reconfiguration in Dataflow Computing
R. CATTANEO, N. Xinyu, C. Pilato, T. Becker, M. D. Santambrogio, and W. Luk
8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2013
doi > 10.1109/ReCoSoC.2013.6581535
A Flexible Interconnection Structure for FPGA Dataflow Applications
G. Durelli, A. Nacci, R. CATTANEO, C. Pilato, D. Sciuto, and M. D. Santambrogio
IPDPS Workshop on Reconfigurable Architectures (RAW), 2013
doi > 10.1109/IPDPSW.2013.127
An enhanced relocation manager to speedup core allocation in FPGA-based reconfigurable systems
M. D. Santambrogio, F. Cancare, R. CATTANEO, S. Bhandari, and D. Sciuto
IPDPS Workshop on Reconfigurable Architectures (RAW), 2012
doi > 10.1109/IPDPSW.2012.41
Other Works
On The Role Of Polyhedral Analysis In High Performance Reconfigurable Hardware Based Computing Systems
R. CATTANEO
PhD Thesis, 2015
PhD Thesis
Explicitly Isolating Data and Computation in High Level Synthesis: the Role of Polyhedral Framework
R. CATTANEO, G. Pallotta, and M. D. Santambrogio
Poster presentation at ReConFig, 2015
Poster
An ACO-based, Reconfiguration Aware Mapper and Scheduler
R. CATTANEO, C. Pilato, G. C. Durelli, A. A. Nacci, M. D. Santambrogio, and D. Sciuto
Poster presentation at Design Automation Conference (DAC), 2013
Poster